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products and specifications discussed herein ar e subject to change by aptina without notice. MT9V011: 1/4-inch vga digital image sensor features pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 1 ?2004 aptina imaging corporation all rights reserved. 1/4-inch vga digital image sensor MT9V011 for the latest data sheet revision, please refer to aptinas web site: www.aptina.com features ?aptina ? digitalclarity? cmos imaging technology ? ultra low-power, low cost cmos image sensor ? superior low-light performance ? simple two-wire serial interface ? auto black level calibration ? window size: vga, programmable to any smaller format (qvga, cif) ? programmable controls: gain, frame rate, left-right and top-bottom image reversal, window size, and panning applications ? cellular phones ?pdas ?pc cameras ? toys and other battery-powered products ordering information table 1: available part numbers part number description MT9V011p11stc:b 28-pin plcc MT9V011do0stcc82sc1 die table 2: key performance parameters parameter value optical format 1/4-inch (4:3) active imager size 3.58mm(h) x 2.69mm(v), 4.48mm diagonal active pixels 640h x 480v pixel size 5.6 m x 5.6 m color filter array rgb bayer pattern shutter type electronic rolling shutter (ers) maximum data rate/ master clock 13.5 mps/27 mhz frame rate vga (640 x 480) 30 fps at 27 mhz cif (352 x 288) programmable up to 60 fps qvga (320 x 240) programmable up to 90 fps adc resolution 10-bit, on-chip responsivity 2.0 v/lux-sec (550nm) dynamic range 60db snr max 45db supply voltage 2.8v 0.25v power consumption 70mw at 2.8v, 27 mhz, 30 fps operating temperature C20c to +60c packaging 28-pin plcc
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_plcc_ds - rev. c 6/10 en 2 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 pixel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 pixel array structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 output data timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 frame timing formulas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 serial bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 bus idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 start bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 slave address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 data bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 no-acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 two-wire serial interface sample read and write sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 16-bit write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 eight-bit write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 eight-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 window control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 blanking control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 pixel integration control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 pixel clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 digital zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 true decimation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 column mirror image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 row mirror image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 column and row skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 line valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 recommdended gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 propagation delays for pixclk and data out signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 propagation delays for frame_valid and line_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 two-wire serial bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_plcc_ds - rev. c 6/10 en 3 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor list of tables table 1: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 3: frame time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 4: constant value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 5: frame time?master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 6: vertical blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 7: recommended gain settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 8: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 9: ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_plcc_ds - rev.c 6/10 en 4 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor list of figures figure 1: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 2: typical configuration (connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 3: 28-pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 4: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 5: pixel color pattern detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 6: spatial illustration of image re adout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 7: timing example of pixel data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 8: row timing and frame_valid/line_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 9: timing diagram showing a write to reg0x09 with the va lue 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 10: timing diagram showing a read from reg0x09; return ed value 0x0284 . . . . . . . . . . . . . . . . . . . . . . .15 figure 11: timing diagram showing a write to reg0x09 with the value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6 figure 12: timing diagram showing a read from reg0x09; return ed value 0x0284 . . . . . . . . . . . . . . . . . . . . . . .16 figure 13: readout of 4 pixels in normal and zoom 2x output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 14: readout of 8 pixels in normal and 2x decimation outp ut mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 15: readout of 6 pixels in normal and column mirror outp ut mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 16: readout of 6 rows in normal and row mirror output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 17: readout of 8 pixels in normal and column skip outp ut mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 18: different line valid formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 19: propagation delays for pixclk and data out signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 20: propagation delays for frame_vali d and line_valid signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 4 figure 21: data output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 22: serial host interface start condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 23: serial host interface stop condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 24: serial host interface data timing for write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 25: serial host interface data timing for read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 26: acknowledge signal timing after an 8-bit write to th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 27: acknowledge signal timing after an 8-bit read from th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 28: spectral response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 29: image center offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 30: 28-pin plcc package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 5 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor general description the aptina? MT9V011 is a 1/4-inch vga-fo rmat cmos active-pixel digital image sensor. the active imaging pixel array is 649h x 489v. it incorporates sophisticated camera functions on-chip such as windowing, column and row mirroring. it is program- mable through a simple two-wire serial bus interface and has very low power consump- tion. the MT9V011 features digitalclarity?aptina?s breakthrough low-noise cmos imaging technology that achieves ccd image quality (based on signal-to-noise ratio and low- light sensitivity) while maintaining the inhere nt size, cost and integration advantages of cmos. the sensor can be operated in its default mode or programmed by the user for frame size, exposure, gain setting, and other para meters. the default mode outputs a vga-size image at 30 frames per second (fps). an on-chip analog -to-digital converter (adc) provides 10 bits per pixel. frame_valid and line_valid signals are output on dedi- cated pins, along with a pixel clock wh ich is synchronous with valid data. figure 1: block diagram active-pixel sensor (aps) array 668h x 496v serial i/o data out sync signals timing and control control register analog processing adc
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 6 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor figure 2: typical configuration (connection) note: 1.5k resistor value is recommended, but may be higher for slower two-wire speed. d out (9:0) frame_valid line_valid pixclk reset_bar s data sclk clkin scan_en oe_bar standby d gnd a gnd v dd v aa vaapix d gnd a gnd v dd v aa 1.5k 10f 1k master clock two-wire serial bus 1.5k
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 7 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor figure 3: 28-pinout diagram table 2: pin description pin number name type description 12 v aa power analog power (2.8v). 14 vaapix power pixel power (2.8v). 1v dd power digital power supply (2.8v). 28 d gnd ground digital ground. 11, 13 a gnd ground analog ground. 14 clkin input master clock into sensor (27 mhz maximum). 19 oe_bar input output_enable_bar pin. when high: disables the pixel data output drivers. 16 reset_bar input asynchronous reset of sensor when low. all registers assume factory defaults. 15 scan_en input tie to digital ground. 8 sclk input serial clock. 17 standby input when high: disables the imager. 9s data bidirectional serial data i/o. 3d out 0 output pixel data output bit 0, d0 (lsb). 2d out 1 output pixel data output bit 1, d1. 27 d out 2 output pixel data output bit 2, d2. 26 d out 3 output pixel data output bit 3, d3. clkin d out 0 d out 1 v dd d gnd d out 2 d out 3 v aa a gnd vaapix scan_en reset_bar standby nc 12 13 14 15 16 17 18 4 3 2 1 28 27 26 111098765 pixclk frame_valid line_valid sclk sdata nc a gnd 19 20 21 22 23 24 25 d out 4 d out 5 d out 6 d out 7 d out 8 d out 9 oe_bar sensor chip
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 8 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor 25 d out 4 output pixel data output bit 4, d4. 24 d out 5 output pixel data output bit 5, d5. 23 d out 6 output pixel data output bit 6, d6. 22 d out 7 output pixel data output bit 7, d7. 21 d out 8 output pixel data output bit 8, d8. 20 d out 9 output pixel data output bit 9, d9 (msb). 6 frame_valid output active high during frame of valid pixel data. 7 line_valid output active high during line of selectable valid pixel data (see reg0x20 for options). 5 pixclk output pixel clock output. pixel data outputs are valid during rising edge of this clock. frequency = 1/2 (master clock). 10, 18 nc ? no connect. table 2: pin description (continued) pin number name type description
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 9 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor pixel data format pixel array structure the MT9V011?s pixel array is 668 columns by 496 rows. the first 18 columns and the first 6 rows of pixels are optically black and can be used to monitor the black level. the last column and the last row of pixels are also optically black. the black row data is used internally for automatic black level adjustment. there are 649 columns by 489 rows of optically active pixels, which provides a four-pixel boundary around the vga (640 x 480) image to avoid boundary affects during co lor interpolation and correction. the addi- tional active column and addi tional active row are used to allow horizontally and verti- cally mirrored readout to also start on the same color pixel, as shown in figure 4. figure 4: pixel array description the MT9V011 uses the rgb bayer color pattern. even numbered rows contain green and red color pixels, and odd numbered rows contain blue and green color pixels. likewise, even numbered columns contain green and blue color pixels, and odd numbered columns contain red and green color pixels. figure 5: pixel color pattern detail (top right corner) output data format the MT9V011 image data is read-out in a progressive scan. valid image data is surrounded by horizontal and vertical blan king, as shown in figure 6. the amount of horizontal and vertical blanking is pr ogrammable through reg0x05 and reg0x06, respectively. line_valid is high during the shaded region of the figure. see ?output data timing? on page 11 for the de scription of frame_valid timing. (667,495) 18 black columns 1 black row 6 black rows (0, 0) 1 black column vga (640 x 480) + 4 pixel boundary for color correction + additional active column + additional active row = 649 x 489 active pixels b g b g b g b r b g g r g r g g g b b r b g g r g r g g g b b r b g g r g r g g g b black pixels column readout dire ction row readout direction pixel (18, 6) (first optical clear pixel)
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 10 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor figure 6: spatial illustration of image readout p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 11 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor output data timing the data output of the MT9V011 is sync hronized with the pixclk output. when line_valid is high, one 10-bit pixel datum is output every pixclk period. figure 7: timing example of pixel data the rising edges of the pixclk signal are no minally timed to occur one-half of a master clock period after the d out edges. this allows pixclk to be used as a clock to latch the data. the pixclk is high for one complete master clock period and then low for one complete master clock period. it is contin uously enabled, even during the blanking period. the MT9V011 can be programmed to move the pixclk edge relative to the d out transitions from +1 to -1 master clock, in step s of one-half of a master clock. this can be achieved by programming the corresponding bits in reg0x07. the parameters p, a, and q in figure 8 are defined in table 3. figure 8: row timing and frame_valid/line_valid signals line_valid pixclk d out9 -d out0 . . . . . . . . . . . . . . . . p 0 (9:0) p 1 (9:0) p2 (9:0) p 3 (9:0) p 4 (9:0) p n-1 (9:0) p n (9:0) valid image data blanking blanking p a q a q a p . . . . . . . . . number of master clocks frame_valid line_valid
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 12 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor frame timing formulas the constant 113 in the formulas in table 3 is the constant value in default mode, when 8 dark columns are read out through reg0x 30. the constant follows the dark columns read out as shown in table 4. sensor timing is shown above in terms of pixel clock and master clock cycles (please refer to figure 7). the recommended master clock frequency is 27 mhz. table 4: constant value the vertical blanking and total frame time eq uations assume that the number of integra- tion rows (bits 11 through 0 of reg0x09) is le ss than the number of active plus blanking rows (reg0x03 + 1 + reg0x06 + 1). if this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in table 5. table 3: frame time parameter name equation default timing at 27 mhz a active data time (reg0x04 + 1) x (reg0x0a + 2) 640 pixel clocks = 1280 master = 47.4 s p frame start/end blanking 6 x (reg0x0a + 2) 6 pixel clocks = 12 master = 0.44 s q horizontal blanking (113 + reg0x05) x (reg0x0a + 2) (minimum reg0x05 value = 9) 244 pixel clocks = 488 master = 18.07 s a+q row time (reg0x04 + 1 + 113 + reg0x05) x (reg0x0a + 2) 884 pixel clocks = 1,768 master = 65.48 s v vertical blanking (reg0x06 + 1) x (a + q) + (q - 2 x p) 25,868 pixel clocks = 51,736 master = 1.92 s n rows x (a + q) frame valid time (reg0x03 + 1) x (a + q) - (q - 2 x p) 424,088 pixel clocks = 848,176 master = 31.41 s f total frame time (reg0x03 + 1 + reg0x06 + 1) x (a + q) 449,956 pixel clocks = 899,912 master = 33.33 s reg 0x30, bit 1:0 constant 1x 121 for 16 columns 01 113 for 8 columns 00 107 for no dark columns read, no row-wise noise correction applied table 5: frame time ? master clock parameter name equation (master clock) default timing v vertical blanking (long integration time) (reg0x09 - reg0x03) x (a + q) + (q - 2 x p) 25,868 pixel clocks = 51,736 master = 1.92 ms f total frame time (long integration time) (reg0x09 + 1) x (a + q) 449,956 pixel clocks = 899,912 master = 33.33ms
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 13 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor serial bus description registers are written to and read from the MT9V011 through the two-wire serial inter- face bus. the sensor is a serial interface slave and is controlled by the serial clock (sclk), which is driven by the serial interface mast er. data is transferred into and out through the MT9V011 serial data (s data ) line. the s data line is pulled up to v dd off-chip by a 1.5k resistor. either the slave or master device can pull the sdata line down?the serial interface protocol determines wh ich device is allowed to pull the s data line down at any given time. the registers are 16 bits wi de, and can be accessed through 16- or 8-bit two-wire serial bus sequences. protocol the two-wire serial interface defines several different transmission codes, as follows: ?a start bit ? the slave device 8-bit address ? a(n) (no) acknowledge bit ? an 8-bit message ?a stop bit sequence a typical read or write sequence begins by th e master sending a start bit. after the start bit, the master sends the slave device?s 8-bi t address. the last bit of the address deter- mines if the request will be a read or a writ e, where a ?0? indicates a write and a ?1? indi- cates a read. the slave device acknowledges its address by sending an acknowledge bit back to the master. if the request was a write, the master then transfers the 8-bit register address to which a write should take place. the sl ave sends an acknowledge bit to indicate that the register address has been received. the master then tr ansfers the data eight bits at a time, with the slave sending an acknowledge bit after each eight bits. the MT9V011 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. after 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register addr ess. the master stops writing by sending a start or stop bit. a typical read sequence is executed as follows. first the master sends the write-mode slave address and 8-bit register address, just as in the write request. the master then sends a start bit and the read-mode slave address. the master then clocks out the register data eight bits at a time. the mast er sends an acknowledge bit after each 8-bit transfer. the register address is auto-incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. the MT9V011 allows for 8-bit data transfers through the two-wire serial interface by writing (or reading) the most significant eight bits to th e register and then writing (or reading) the least significant eight bits to reg0x80 (128). bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits.
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 14 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high. stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high. slave address the 8-bit address of a two-wire serial interfac e device consists of seven bits of address and 1 bit of direction. a ?0? in the lsb of the address indicates write mode, and a ?1? indicates read mode. the write address of the sensor is 0xba, while the read address is 0xbb. data bit transfer one data bit is transferred during each clock pulse. the two-wire serial interface clock pulse is provided by the master. the data must be stable during the high period of the serial clock?it can only change when the two-wire serial interface clock is low. data is transferred eight bits at a time, followed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing, or the slave when reading) re leases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence.
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 15 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor two-wire serial interface sample read and write sequences 16-bit write sequence a typical write sequence for writing 16 bits to a register is shown in figure 9. a start bit given by the master, followed by the write address, starts the sequence. the image sensor will then give an acknowledge bit and expects the register address to come first, followed by the 16-bit data. after each 8-bit the image se nsor will give an acknowledge bit. all 16 bits must be written before the register will be updated. after 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register. the master stops writ ing by sending a start or stop bit. figure 9: timing diagram showing a write to reg0x09 with the value 0x0284 16-bit read sequence a typical read sequence is shown in figure 10. first the master has to write the register address, as in a write sequence. then a start bit and the read address specifies that a read is about to happen from the register. the master then clocks out the register data eight bits at a time. the master sends an acknowled ge bit after each 8-bit transfer. the register address is auto-incremented af ter every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. figure 10: timing diagram showing a read from reg0x09; returned value 0x0284 sclk sdata start ack 0xba addr ack ack ack stop reg 0x09 1000 0100 0000 0010 sclk sdata start ack 0xba addr 0xbb addr 0000 0010 reg 0x09 ack ack ack stop 1000 0100 nack start
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 16 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor eight-bit write sequence to be able to write one byte at a time to th e register a special register address is added. the 8-bit write is done by first writing the upper eight bits to the desired register and then writing the lower eight bits to the specia l register address (reg0x80). the register is not updated until all 16 bits have been written. it is not possible to just update half of a register. in figure 11 a typical sequence for 8-bit writing is shown. the second byte is written to the special register (reg 0x80). figure 11: timing diagram showing a write to reg0x09 with the value 0x0284 eight-bit read sequence to read one byte at a time the same special register address is used for the lower byte. the upper eight bits are read from the desired register. by following this with a read from the special register (reg0x80) the lower eight bits are accessed (figure 12). the master sets the no-acknowledge bits shown. figure 12: timing diagram showing a read from reg0x09; returned value 0x0284 stop reg0x80 ack start 0xba addr ack sdata sclk ack ack ack ack reg0x09 0xba addr 0000 0010 1000 0100 start start 0xbb addr sdata sclk stop nack ack ack ack reg0x09 start 0xba addr 0000 0010 start 0xbb addr sdata sclk nack ack ack ack reg0x80 start 0xba addr 1000 0100
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 17 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor feature description window control reg0x01 row start, reg0x02 column start, reg0x03 window height (row size), and reg0x04 window width (column size) these registers control the size and starting coordinates of the window. by changing these registers, any image fo rmat smaller than or equal to vga can be specified. blanking control reg0x05 horizontal blanking, and reg0x06 vertical blanking blanking control: these registers control the blanking time in a row (called column fill-in or horizontal blanking) and between frames (vertical blanking). ? horizontal blanking is specified in terms of pixel clocks. ? vertical blanking is specified in terms of row readout times. (the programmed value is one less than the actual value.) the actual imager timing ca n be calculated using table 3 on page 12 which describes "row timing and frame_valid/line_valid signals.? the number of dark rows read out depends on the vertical blanking set as shown in the table 6. pixel integration control reg0x09 shutter width, and reg0x0c shutter delay these registers (along with the window size and horizontal blanking registers) control the integration time for the pixels. reg0x09: number of rows of integration, default = 0x01fc (508) reg0x0c: reset delay, default = 0x0000 (0). this is the number of master clocks that the timing and control logic waits before asserting the reset for a given row. the actual total integration time, t int, is: t int = reg0x09 x row time - overhead time - reset delay, where: row time = (reg0x04 + 1 + 113 + reg0x05) x (reg0x0a + 2) master clock periods overhead time = k x 57 master clock periods reset delay = k x reg0x0c master clock periods if the value in reg0x0c exceeds (row time - 444)/k master clock cycles, the row time will be extended by (k x reg0x0c - (row time - 444)) clock cycles. table 6: vertical blanking reg0x06 # dark rows 00 1-2 2 3+ 4
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 18 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor where : k = 4 when reg0x07[4] = 0, and k = 2 when reg0x07[4] = 1 in this expression the row time term corresponds to the number of rows integrated. the overhead time is the time between the read cycle and the reset cycle, and the final term is the effect of the reset delay. typically, the value of reg0x09 (shutter widt h) is limited to the number of rows per frame (which includes vertical blanking rows), such that the frame rate is not affected by the integration time. if reg0x09 is increased beyond the total number of rows per frame, the MT9V011 will add additional blanking rows as needed. a second constraint is that t int must be adjusted to avoid banding in the image from light flicker. under 60 hz flicker, this means t int must be a multiple of 1/120 of a second. under 50 hz flicker, t int must be a multiple of 1/100 of a second. pixel clock speed reg0x0a pixel clock speed the pixel clock speed is set by reg0x0a. the pixel clock period will be the number set plus two master clock cycles. the default value is 0, which is equal to 2 master clock cycles. with a master clock frequency of 27 mhz the pixclk frequency will be 13.5 mhz. the pixel clock out can be shif ted relative to the data out by setting bit 8-11 of reg0x07 appropriately. reset reg0x0d reset this register is used to reset the sensor to its default, power-up state. to reset the MT9V011, first write a ?1? into bit 0 of this re gister, then write a ?0? into bit 0 to resume operation. digital zoom reg0x1e digital zoom/true decimation in zoom mode, the pixel data rate is slowed down by a factor of either 2 or 4, and either 1 or 3 additional blank rows are added between ea ch output row. this is designed to give the controller logic time to repeat data to fill in a window that is either 2 or 4 times larger with repeated data. the pixel clock speed is not affected by this operation, and the output data for each pixel is valid for either 2 or 4 pixel clocks. in zoom by 2 mode, every row is followed by a blank row (with its own line valid, but all data bits = 0) of equal time. in zoom by 4 mode, every row is followed by three blank rows. the comb ination of this register and an appropriate change to the window sizing registers allows the user to zoom to a region of interest without affecting the frame rate.
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 19 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor figure 13: readout of 4 pixels in normal and zoom 2x output mode true decimation mode reg0x1e digital zoom/true decimation true decimation mode is intended for use in sensors without color filtering. there are three modes with different amount of decima tion. in decimate 2x every other column and row are skipped. in decimate 4x three rows/columns will be skipped for every row/ column read out, and in decimate 8x seven rows/columns will be skipped for every row/ column read out. decimate 2x is shown in figure 14. in decimation mode the global gain register should be used to set the gain. figure 14: readout of 8 pixels in normal and 2x decimation output mode read mode column mirror image by setting bits 14 and 5 of reg0x20 the readou t order of the columns will be reversed, as shown in figure 15. figure 15: readout of 6 pixels in normal and column mirror output mode line_valid d out9 -d out0 pixclk normal readout line_valid pixclk zoom 2x readout g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) r1 (9:0) g1 (9:0) r0 (9:0) g0 (9:0) d out9 -d out0 p0 (9:0) p1 (9:0) p2 (9:0) p3 (9:0) p4 (9:0) p5 (9:0) p6 (9:0) p7 (9:0) p0 (9:0) p2 (9:0) p4 (9:0) p6 (9:0) line_valid d out9- d out0 normal readout line_valid d out9 -d out0 decimate 2x readout line_valid d out9 -d out0 normal readout d out9 -d out0 reverse readout g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) r2 (9:0) g3 (9:0) r2 (9:0) g2 (9:0) r1 (9:0) g1 (9:0) r0 (9:0)
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 20 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor row mirror image by setting bits 15 and 7 of reg0x20 the read out order of the rows will be reversed, as shown in figure 16. figure 16: readout of 6 rows in normal and row mirror output mode column and row skip by setting bit 3 of reg0x20 only half of the columns set will be read out, as shown in figure 17. the row skip works in the same wa y and will only read out two out of four rows. for both row and column skip the number of rows/columns read out will be half of what is set in reg0x03 and reg0x04. figure 17: readout of 8 pixels in normal and column skip output mode line valid by setting bit 9 and 10 of reg0x20 the line valid signal can get three different output formats. the formats are shown in figure 18 when reading out four rows and two vertical blanking rows. in the last format the line valid signal is the xor between the continu- ously line valid signal and the frame valid signal. figure 18: different line valid formats frame_valid dout9-dout0 row0 (9:0) row1 (9:0) row2 (9:0) row3 (9:0) row4 (9:0) row5 (9:0) normal readout dout9-dout0 (9:0) (9:0) (9:0) (9:0) (9:0) (9:0) reverse readout row 6 row5 row4 row3 row2 row1 d out9-dout0 g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) r2 (9:0) l ine_v alid n ormal readout d out9-dout0 column skip readout g3 (9:0) r3 (9:0) g0 (9:0) r0 (9:0) g2 (9:0) r2 (9:0) l ine_v alid default frame_valid line_valid continuously frame_valid line_valid xor frame_valid line_valid
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 21 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor recommdended gain settings the gains for green1, blue, red, and green2 pixels are set by registers reg0x2b, reg0x2c, reg0x2d, and reg0x2d, respectively. gain can also be set globally by reg0x35. the analog gain is set by bits[8:0] of the corresponding register as following: gain = (bit[8] + 1) x (bit[7] + 1) x (bit[6:0]/32) digital gain is set by bits 9 and 10 of the same registers. the analog gain circuitry (pre-adc) is design ed to offer signal gains from 1 to 15.875. the minimum gain of 1 (register set to 0x00 20) corresponds to the lowest setting where the pixel signal is guaranteed to saturate the adc under all specified operating condi- tions. any reduction of the gain below this va lue may cause the sensor to saturate at adc output values less than the maximum, under certain conditions. it is recommended that this guideline be followed at all times. since bits 7 and 8 of the gain registers are multiplicative factors for the gain settings, there are alternative ways of achieving certain gains. some settings offer superior noise performance to others, while the same overal l gain. table 7 lists the recommended gain settings. table 7: recommended gain settings desired gain recommended settings (gain registers) conversion formula (arithmetic) 1.000 to 1.969 0x0020 to 0x003f (register value)/32 2.000 to 7.938 0x00a0 to 0x00ff (register value - 128)/16 8.000 to 15.875 0x01c0 to 0x01ff (register value - 384)/8
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 22 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor electrical specifications note: 1. to place the chip in standby mode, first raise standby to v dd , then wait two master clock cycles before turning off the master clock. two master clock cycles are required to place the analog circuitry into standby, low-power mode. 2. when standby is de-asserted, standby mode is exited immediately (within several master clocks), but the current frame and the next two frames will be invalid. the fourth frame will contain a valid image. table 8: dc electrical characteristics (v dd = v aa = 2.8 0.25v; t a = ambient = 25 c; 30 fps at 27 mhz) symbol definition condition min typ max unit notes v ih input high voltage v dd -0.25 v dd +0.25 v v il input low voltage -0.3 0.8 v i in input leakage current no pull-up resistor; v in = v dd or v gnd -5 5 a v oh output high voltage v dd -0.2 v v ol output low voltage 0.2 v i oh output high current 5.0 a i ol output low current 5.0 a i oz tri-state output leakage current 5.0 a i aa analog operating current clkin = 27 mhz; default setting, c load = 10pf 14.0 20.0 28.0 ma i dd digital operating current clkin = 27 mhz; default setting, c load = 10pf 3.0 5.0 8.0 ma i aa standby analog standby supply current stdby = v dd 0.0 0.0 5.0 a1, 2 i dd standby digital standby supply current stdby = v dd 0.0 1.0 5.0 a1, 2
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 23 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor notes: 1. for 30 fps operation with a 27 mhz clock, it is very important to have a precise duty cycle equal to 50%. with a slower frame rate and a slower clock the clock duty cycle can be relaxed. table 9: ac electrical characteristics (v dd = v aa = 2.8 0.25v; t a = ambient = 25 c) symbol definition condition min typ max unit notes f clkin input clock frequency 27 27 mhz clock duty cycle 45 50 55 % 1 t r input clock rise time 2.5 ns t f input clock fall time 2.0 ns t plh p t phl p clkin to pixclk propagation delay: low-to-high high-to-low c load = 10pf 12.0 10.0 ns t dsetup t dhold pixclk to d out (9:0) setup time hold time c load = 10pf 15.0 14.0 ns t oh data hold time from clkin 9.0 ns t plh f , l t phl f , l clkin to frame_valid and line_valid propagation delay: low-to-high, high-to-low c load = 10pf 12.0 11.0 ns t plh d t phl d clkin to d out (9:0) propagation delay: low-to-high, high-to-low c load = 10pf 7.5 7.0 ns t out routput rise time c load = 10pf 7.0 ns t out f output fall time c load = 10pf 9.0 ns
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 24 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor propagation delays for pixclk and data out signals the typical output delay, relative to the mast er clock edge, is 7.5 ns. note that the data outputs change on the falling edge of the mast er clock, with the pixel clock rising on the subsequent rising edge of the master clock. propagation delays for frame_valid and line_valid signals the line_valid and frame_valid signals ch ange on the same falling master clock edge as the data output. the line_valid go es high on the same falling master clock edge as the output of the first valid pixel' s data and returns low on the same master clock falling edge as the end of the ou tput of the last valid pixel's data. as shown in the ?output data timing? on page 11, frame_valid goes high 6 pixel clocks prior to the time that the first line_valid goes high. it returns low at a time corresponding to 6 pixel clocks afte r the last line_valid goes low. figure 19: propagation delays for pixclk and data out signals figure 20: propagation delays for frame_valid and line_valid signals d out (9:0) d out (9:0) d out (9:0) d out (9:0) d out (9:0) clkin pixclk t plh d , t phl d t plh p t r t f t phl p t oh clkin frame_valid line_valid clkin frame_valid line_valid t plh f,l t phl f,l
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 25 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor figure 21: data output timing diagram pixclk = max. 27 mhz t fvsetup = / setup time for frame_valid before rising edge of pixclk / = 18ns t fvhold = / hold time for frame_valid after falling edge of pixclk / = 18ns t lvsetup = / setup time for line_valid before rising edge of pixclk / = 18ns t lvhold = / hold time for line_valid after falling edge of pixclk / = 18ns t dsetup = / setup time for d out before rising edge of pixclk / = 13ns t dhold = / hold time for d out after falling edge of pixclk / = 13ns frame start: ff00 00a0 line start: ff00 0080 line end: ff00 0090 frame end: ff00 0010 pixclk frame_valid line_valid d out (9:0) t dvsetup t dvhold t fvhold t lvhold t fvsetup t lvsetup
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 26 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor two-wire serial bus timing the two-wire serial bus operation requir es certain minimum master clock cycles between transitions. these are specified in the following diagrams in master clock cycles. figure 22: serial host interface start condition timing figure 23: serial host interface stop condition timing note: all timing are in units of master clock cycle. figure 24: serial host interface data timing for write note: s data is driven by an off-chip transmitter. figure 25: serial host interface data timing for read note: s data is pulled low by the sensor, or allowed to be pulled high by a pull-up resistor off-chip. sclk 5 s data 4 sclk 5 sdata 4 sclk 4 sdata 4 sclk 5 sdata
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 27 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor figure 26: acknowledge signal timing after an 8-bit write to the sensor figure 27: acknowledge signal timing after an 8-bit read from the sensor note: after a read, the master receiver must pull down s data to acknowledge receipt of data bits. when read sequence is complete, the master must generate a no acknowledge by leaving s data to float high. on the following cycle a start or stop bit may be used. figure 28: spectral response sclk sensor pulls down sdata pin 6 sdata 3 sclk sensor tri-states sdata pin (turns off pull down) 7 sdata 6 0.0 0.2 0.4 0.6 0.8 1.0 1.2 350 450 550 650 750 850 950 1050 wavelength (nm) relative response blue green (b) green (r) red relative spectral response
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 28 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor figure 29: image center offset note: not to scale. image center chip center pixel array pixel (0,0) 697.4um 14.6um sensor chip
pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 29 ?2009 aptina imaging corporation. all rights reserved. MT9V011: 1/4-inch vga digital image sensor figure 30: 28-pin plcc package outline drawing note: all dimensions are in millimeters. 2.35 0.15 seating plane section aCa 0.08 0.70 0.05 1 28 1.27 typ a 7.62 lid material: borosilicate glass lead finish: gold plating, 20 micro inches minimum thickness substrate material: fr4 resin 1.27 typ 7.62 a 1.70 0.10 11.43 0.10 0.64 typ 29x r0.225 27x 1.27 2.16 0.350 0.050 1.450 0.075 0.55 0.05 8x 1.905 0.100 11.43 0.10 0.08
10 eunos road 8 13-40, singapore post center, singapore 408600 prodmktg@aptina.com www.aptina.com aptina, aptina imaging, digitalclarity, and the aptina logo are the property of aptina imaging corporation all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. MT9V011: 1/4-inch vga digital image sensor pdf:9441249584/source:7716559265 aptina reserves the right to change products or specifications without notice. MT9V011_pllc_ds - rev. c 6/10 en 30 ?2009 aptina imaging corporation all rights reserved. revision history rev. c ......................................................................................................................... .......................................................6/10 ? updated to non-confidentail rev. b ......................................................................................................................... .......................................................5/10 ? updated to aptina template rev a, preliminary ............................................................................................................. ............................................12/04 ? initial release of document

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